TECHNICAL CONTENT

Who Needs a Hypervisor?

_______________ The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to: Partition multicore processors into virtual machines; an elegant way to... Read More

What is Cache Coloring and How Does it Work?

_______________ There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time... Read More

Challenges Building Safe Multicore Systems

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What Is A Separation Kernel?

_______________ Having built both separation kernels and real-time operating systems—and supported customers using both across a wide range of industries—we are familiar with the pros and cons of each software technology, as well as their security,... Read More

Field Notes: Safety-Critical Systems Symposium 2020

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TC-16/51: Adding Bottom Up Interference Analysis for MCPs

_______________ I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51. But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective. In their own... Read More

What is SR-IOV and Why is It Important for embedded devices?

Single Root I/O Virtualization (SR-IOV) is the complex name for a technology beginning to find its way into embedded devices. SR-IOV is a hardware standard that allows a PCI Express device – typically a network interface card (NIC) – to present... Read More

What is the Cost of a Board Support Package?

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Design Prevails: Protecting Systems from Meltdown and Spectre

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