22 min read

Challenges Building Safe Multicore Systems

By Tim Loveless | Principal Solutions Architect on Jun 15, 2020 8:12:09 AM

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At the time of writing, no multicore safety critical software systems exist. That is, no system that utilizes a multi-core processor to execute multiple applications in parallel has been certified for flight by the Federal Aviation Administration (FAA) in the US or by the European Union Aviation Safety Agency (EASA). As such, safety critical avionics systems are missing out on the advances in compute performance, power consumption, and miniaturization enjoyed by laptop, smartphone, and internet users worldwide.

Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
19 min read

What Is A Separation Kernel?

By Tim Loveless | Principal Solutions Architect on Mar 22, 2020 12:02:33 PM

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Having built both separation kernels and real-time operating systems—and supported customers using both across a wide range of industries—we are familiar with the pros and cons of each software technology, as well as their security, safety, reliability, and adaptability impact on complex system designs. Yet despite providing strong security and safety benefits and being the foundation of some of the world’s largest mission-critical systems, separation kernels remain largely unknown and poorly understood. In this article, we hope to:

  1. Bring some clarity to the topic of separation kernels vs. real-time operating systems (RTOSes) and embedded hypervisors
  2. Discuss the benefits and drawbacks of using a separation kernel as the software foundation of your embedded systems design
  3. Introduce LynxSecure®, our own separation kernel
Topics: Safety Certification MCP Least Privilege Systems Architecture Security Trusted Codebase architecture linux rtos embedded systems hardware vulnerabilities development real-time LynxSecure separation kernel hypervisors virtualization
3 min read

Field Notes: Safety-Critical Systems Symposium 2020

By Tim Loveless | Principal Solutions Architect on Feb 24, 2020 12:34:50 PM

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Topics: Multi-core Avionics Demo Cache-partitioning Lynx MOSA.ic™ Events FAA Safety TC-16/51 CAST-32A Certification MCP Systems Architecture Cache Allocation Technology embedded systems hardware development Technical Blog Standards
4 min read

TC-16/51: Adding Bottom Up Interference Analysis for MCPs

By Mark Brown | Systems Architect on Jan 28, 2020 2:20:00 PM

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I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51.  But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective.  In their own words, here's their proposal to add "bottom up" analysis to aircraft safety certifications on Multi-Core Processors (MCP):

Topics: Multi-core Avionics FAA Safety TC-16/51 CAST-32A Certification MCP Systems Architecture rtos embedded systems partitioning hardware development real-time Technical Blog
5 min read

What is SR-IOV and Why is It Important for embedded devices?

By Tim Loveless | Principal Solutions Architect on Oct 7, 2019 2:09:00 PM

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Topics: Multi-core Demo Safety MCP Systems Architecture embedded systems hardware development Single-root IO Virtualization SR-IOV PCI-E
12 min read

What is the Cost of a Board Support Package?

By Tim Loveless | Principal Solutions Architect on Oct 1, 2019 10:35:00 AM

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Topics: Multicore Certification MCP embedded systems TCO hardware development BSPs board support costs
3 min read

Design Prevails: Protecting Systems from Meltdown and Spectre

By Will Keegan | CTO on Feb 19, 2018 10:21:00 AM

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Topics: Press Release Least Privilege Systems Architecture Security spectre CVEs hardware side channels privilege escalation meltdown vulnerabilities