Tim Loveless | Principal Solutions Architect

Tim Loveless | Principal Solutions Architect

Tim Loveless has 25 years’ embedded industry experience in the fields of real-time operating systems, safety critical systems, JTAG tools, and embedded linux. Before joining Lynx Software Technologies as Principal Solutions Architect, he worked as an FAE for Wind River UK, for Intel’s Internet of Things Group and as European Aerospace and Defence FAE Manager for Wind River. Tim’s interests include computer security and macroeconomics. He enjoys podcasts, cycling, and running, while skiing and paddle boarding are rare treats.

Recent posts by Tim Loveless | Principal Solutions Architect

12 min read

Single Root I/O Virtualization (SR-IOV) -Pt 2- LynxOS-178 10G network benchmarkS

By Tim Loveless | Principal Solutions Architect on Mar 16, 2021 12:33:11 PM

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Single Root I/O Virtualization (SR-IOV) virtualizes network interface cards (NICs) to allow a single NIC to present itself as dozens of virtual NICs to a hypervisor. It is a hardware standard, part of the PCI-SIG (Peripheral Component Interconnect - Special Interest Group) and is heavily used in data centers. It is a key software defined networking (SDN) component that allows data centers to efficiently host internet servers as virtual machines (VMs). SR-IOV provides a pool of hardware virtualized NICs that a cloud computing platform such as OpenStack dynamically assigns to VMs as they are launched. This infrastructure uses Linux orchestration platforms and mainly Linux based enterprise guest OSs.

In our first blog post on the topic (Part I), we saw that the Intel® Atom® C3858 (Denverton) Processor has 4 built-in X550 NICs that present 256 virtual NICs. LynxSecure was used to build a system with 5 Buildroot Linux guests, 4 of which used virtual SR-IOV NICS. This article (Part II), takes the next step and illustrates how to build a system with 3 LynxOS-178 RTOS guests and a Buildroot Linux. LynxSecure is used to assign 14 SR-IOV NICs to the guests before we run benchmarks to measure the overhead of SR-IOV virtual networking. These are high performance 10G bit/sec NICs, so the benchmarks are also an interesting comparison of Linux vs LynxOS-178 networking performance for UDP and TCP at various packet sizes.

Topics: Multicore Safety MCP embedded systems hardware development Single-root IO Virtualization hypervisors virtualization software certifications Virtual Machines 10G Benchmark
10 min read

Who Needs a Hypervisor?

By Tim Loveless | Principal Solutions Architect on Feb 25, 2021 12:59:58 PM

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The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to:

  1. Partition multicore processors into virtual machines; an elegant way to consolidate OSs
  2. Isolate guests; to improve security and safety
  3. Oversubscribe high performance multicore processors; use time slicing to host more OSes than cores
Topics: Multicore Safety CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
11 min read

What is Cache Coloring and How Does it Work?

By Tim Loveless | Principal Solutions Architect on Feb 5, 2021 11:52:40 AM

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There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time systems. Here we discuss a proposed solution, called cache coloring. Opinions on cache coloring are mixed, sometimes extreme, and the implementation can be difficult and risky. This article aims to demystify cache coloring by clarifying exactly how it works. We hope that the example using a real Intel processor and accurate diagrams allows you to grasp cache coloring without getting lost in lines, sets and ways.

Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
4 min read

Intel’s first DO-254 hardware certification evidence – it’s on a MultiCore

By Tim Loveless | Principal Solutions Architect on Dec 18, 2020 10:52:15 AM

WELL DONE, INTEL®!

Over the years I’ve read lots of datasheets. They can sometimes be heavy on marketing buzzwords and prone to sweeping statements that oversell their solutions and gloss over gaps. I read this new Solution Brief from Intel and it stopped me in my tracks. This is the best datasheet I have seen in years. This document lays out the flight safety evidence pack (FSEP) that Intel has created for their Denverton processor. They explain in plain language why the pack was created, for whom and the exact safety standard it applies to. For years Intel have closely guarded their intellectual property which has hampered the use of their processors in aviation. This FSEP overturns that reputation. But there is more: Intel goes further and targets this evidence pack at achieving safety certification of a multi-core processor. Multicore certification is the Holy Grail of the aviation safety industry—a goal everyone is working toward, but at the time of writing, remains unachieved.

25 min read

Challenges Building Safe Multicore Systems

By Tim Loveless | Principal Solutions Architect on Jun 15, 2020 8:12:09 AM

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Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
19 min read

What Is A Separation Kernel?

By Tim Loveless | Principal Solutions Architect on Mar 22, 2020 12:02:33 PM

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Having built both separation kernels and real-time operating systems—and supported customers using both across a wide range of industries—we are familiar with the pros and cons of each software technology, as well as their security, safety, reliability, and adaptability impact on complex system designs. Yet despite providing strong security and safety benefits and being the foundation of some of the world’s largest mission-critical systems, separation kernels remain largely unknown and poorly understood. In this article, we hope to:

  1. Bring some clarity to the topic of separation kernels vs. real-time operating systems (RTOSes) and embedded hypervisors
  2. Discuss the benefits and drawbacks of using a separation kernel as the software foundation of your embedded systems design
  3. Introduce LynxSecure®, our own separation kernel
Topics: Safety Certification MCP Least Privilege Systems Architecture Security Trusted Codebase architecture linux rtos embedded systems hardware vulnerabilities development real-time LynxSecure separation kernel hypervisors virtualization
3 min read

Field Notes: Safety-Critical Systems Symposium 2020

By Tim Loveless | Principal Solutions Architect on Feb 24, 2020 12:34:50 PM

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Topics: Multi-core Avionics Demo Cache-partitioning Lynx MOSA.ic™ Events FAA Safety TC-16/51 CAST-32A Certification MCP Systems Architecture Cache Allocation Technology embedded systems hardware development Technical Blog Standards
20 min read

What Are the Problems with Embedded Linux?

By Tim Loveless | Principal Solutions Architect on Jan 13, 2020 10:24:00 AM

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Topics: linux embedded linux rtos embedded systems development
7 min read

Overarching Properties: An Alternative to DO-178

By Tim Loveless | Principal Solutions Architect on Nov 16, 2019 10:20:00 AM

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Overarching Properties—an alternative design assurance approach to DO-178C—marks the biggest change in airborne software safety certification since DO-178B was unveiled in 1992. Intended to be more efficient and flexible than DO-178C, the approach was introduced as DO-178C and the Overarching Properties Initiative during FAA Chief Scientist George Romanski’s keynote address at the High Integrity Software Conference in Bristol, United Kingdom (UK).

Topics: Avionics FAA Safety Certification
16 min read

How to Choose a Real-Time Operating System

By Tim Loveless | Principal Solutions Architect on Oct 14, 2019 10:32:00 AM

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Choosing an RTOS is not as simple as choosing a car.  We know about cars; we know their strengths and weaknesses and we intuitively understand compromises like performance vs practicality or luxury vs price.  We see all kinds of vehicles on the road, so the range of available cars is obvious. When choosing an RTOS, the middle ground is crowded—dozens of general-purpose RTOSes with broadly similar characteristics compete.  They all have a scheduler, services, libraries, middleware, technical support, and graphical tools. Any one of them could genuinely do a good job and so choosing between them is a mixture of quantitative metrics (like features and price) and qualitative measures (like past-experience, personal-preference, and reputation). 

Topics: Multi-core Avionics Lynx MOSA.ic™ Multicore Safety MCP Systems Architecture Security linux embedded linux rtos embedded systems development real-time