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Multicore safety research from Barcelona Supercomputer Centre (BSC) says that a robustly partitioned hardware and software platform is practically impossible. With today’s multicore processors (MCPs), current RTOS, and hypervisor technology Dr.... Read More

Who Needs a Hypervisor?

_______________ The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to: Partition multicore processors into virtual machines; an elegant way to... Read More

What is Cache Coloring and How Does it Work?

_______________ There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time... Read More

Challenges Building Safe Multicore Systems

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Field Notes: Safety-Critical Systems Symposium 2020

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TC-16/51: Adding Bottom Up Interference Analysis for MCPs

_______________ I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51. But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective. In their own... Read More

CAST-32A: Significance and Implications

_______________ CAST-32A presents the coordinated position of avionics certification authorities regarding Multi-Core Processors (MCPs). While today’s aerospace ecosystem could benefit from the use of MCPs, before CAST-32A was published, FAA/EASA... Read More