11 min read

What is Cache Coloring and How Does it Work?

By Tim Loveless | Principal Solutions Architect on Feb 5, 2021 11:52:40 AM

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There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time systems. Here we discuss a proposed solution, called cache coloring. Opinions on cache coloring are mixed, sometimes extreme, and the implementation can be difficult and risky. This article aims to demystify cache coloring by clarifying exactly how it works. We hope that the example using a real Intel processor and accurate diagrams allows you to grasp cache coloring without getting lost in lines, sets and ways.

Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
25 min read

Challenges Building Safe Multicore Systems

By Tim Loveless | Principal Solutions Architect on Jun 15, 2020 8:12:09 AM

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Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
3 min read

Field Notes: Safety-Critical Systems Symposium 2020

By Tim Loveless | Principal Solutions Architect on Feb 24, 2020 12:34:50 PM

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Topics: Multi-core Avionics Demo Cache-partitioning Lynx MOSA.ic™ Events FAA Safety TC-16/51 CAST-32A Certification MCP Systems Architecture Cache Allocation Technology embedded systems hardware development Technical Blog Standards
4 min read

TC-16/51: Adding Bottom Up Interference Analysis for MCPs

By Mark Brown | Systems Architect on Jan 28, 2020 2:20:00 PM

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I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51.  But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective.  In their own words, here's their proposal to add "bottom up" analysis to aircraft safety certifications on Multi-Core Processors (MCP):

Topics: Multi-core Avionics FAA Safety TC-16/51 CAST-32A Certification MCP Systems Architecture rtos embedded systems partitioning hardware development real-time Technical Blog
8 min read

CAST-32A: Significance and Implications

By Mark Brown | Systems Architect on Nov 15, 2018 10:36:00 AM

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CAST-32A presents the coordinated position of avionics certification authorities regarding Multi-Core Processors (MCPs).  While today’s aerospace ecosystem could benefit from the use of MCPs, before CAST-32A was published, FAA/EASA had not yet devised a means to obtain certification credit for safety-critical software deployed to an MCP.  Toward that end, the CAST-32A position paper identifies topics of concern that could impact the safety, performance, and integrity of DO-178C aviation software deployed to MCP(s). For each topic, the paper provides a rationale that explains why these topics are of concern and proposes objectives to address the concern. (CAST-32A, “Purpose”, p. 3)

Topics: Avionics Multicore FAA Safety TC-16/51 CAST-32A Certification MCP embedded systems development real-time