10 min read

Who Needs a Hypervisor?

By Tim Loveless | Principal Solutions Architect on Feb 25, 2021 12:59:58 PM

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The standard benefits of a hypervisor are well known and often touted. Every RTOS has its hypervisor and they do genuinely help embedded designers to:

  1. Partition multicore processors into virtual machines; an elegant way to consolidate OSs
  2. Isolate guests; to improve security and safety
  3. Oversubscribe high performance multicore processors; use time slicing to host more OSes than cores
Topics: Multicore Safety CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
11 min read

What is Cache Coloring and How Does it Work?

By Tim Loveless | Principal Solutions Architect on Feb 5, 2021 11:52:40 AM

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There are substantial challenges in building secure and safe systems on multicore processors (MCPs). Last level cache contention is undoubtedly the largest source of multicore interference, and a significant challenge for real-time systems. Here we discuss a proposed solution, called cache coloring. Opinions on cache coloring are mixed, sometimes extreme, and the implementation can be difficult and risky. This article aims to demystify cache coloring by clarifying exactly how it works. We hope that the example using a real Intel processor and accurate diagrams allows you to grasp cache coloring without getting lost in lines, sets and ways.

Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178
25 min read

Challenges Building Safe Multicore Systems

By Tim Loveless | Principal Solutions Architect on Jun 15, 2020 8:12:09 AM

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Topics: Multicore Safety TC-16/51 CAST-32A Certification MCP embedded systems hardware development hardware interference software certifications DO-178