Skip to the main content.
CONNECT WITH LYNX
CONNECT WITH LYNX
Learning Center BG 01

Learning Center

Articles, white papers, and technical blog posts. Click on an article to begin searching by topic and subscribe to recieve updates as new content is posted.
8 min read

Adjusting System Functionality and Capabilities in LYNX MOSA.ic
5 min read

Using and Sharing RAM Disks in LYNXOS-178
9 min read

IMPORTANCE OF SYSTEM ARCHITECTURE AND PLATFORM CHOICE ON SAFETY CERTIFICATION
16 min read

ROBUST PARTITIONING IS DEAD – WHAT NOW?
14 min read

Introducing the Z-Application-Bridging the gap between bare metal and rtos
12 min read

Single Root I/O Virtualization (SR-IOV) -Pt 2- LynxOS-178 10G network benchmarkS
10 min read

Who Needs a Hypervisor?
14 min read

Edge Computing is Here. What's Next?
12 min read

What is Cache Coloring and How Does it Work?
6 min read

On reference architectures
4 min read

Intel’s first DO-254 hardware certification evidence – it’s on a MultiCore
5 min read

Conformance vs Compliance – What's in a Word?
19 min read

What is the Cost of a Real-time Operating System (RTOS)?
25 min read

Challenges Building Safe Multicore Systems
3 min read

Best Real-Time Operating System (RTOS) Vendors (2020)
20 min read

What Is A Separation Kernel?
3 min read

Field Notes: Safety-Critical Systems Symposium 2020
4 min read

TC-16/51: Adding Bottom Up Interference Analysis for MCPs
20 min read

What Are the Problems with Embedded Linux?
5 min read

Lynx & ENSCO Demonstrate Avionics Solutions at DSEI JAPAN 2019
7 min read

Overarching Properties: An Alternative to DO-178
21 min read

What Are the Most Popular Real-Time Operating Systems in 2024?
21 min read

Do You Need a Real-Time Operating System?
9 min read

Embedded Best Practices at Arm Tech-con
18 min read

How to Choose a Real-Time Operating System
12 min read

What Are POSIX Processes and Virtual Memory?
6 min read

Realizing modern Automotive Software Environments
5 min read

What is SR-IOV and Why is It Important for embedded devices?
3 min read

Multi-core cache allocation technology (CAT) demo
13 min read

What is the Cost of a Board Support Package?
3 min read

Field Notes: Sept 2019 Face™ TIM
9 min read

What Are the Benefits of POSIX for Embedded Systems?
5 min read

What is a Reusable Software Component?
8 min read

CAST-32A: Significance and Implications
3 min read

Design Prevails: Protecting Systems from Meltdown and Spectre
4 min read

TC-16/51: Adding Bottom Up Interference Analysis for MCPs

By Mark Brown | Systems Architect on Jan 28, 2020 7:54:00 AM

I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51.  But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective.  In their own words, here's their proposal to add "bottom up" analysis to aircraft safety certifications on Multi-Core Processors (MCP):

Topics: Avionics Multicore FAA Safety TC-16/51 CAST-32A Certification MCP
All posts