4 min read
TC-16/51: Adding Bottom Up Interference Analysis for MCPs
By Mark Brown | Systems Architect on Jan 28, 2020 7:54:00 AM
I hadn't heard of "bottom up" avionics certification before I read FAA's TC-16/51. But now, looking back at it, I think the authors from Thales Avionics, including Xavier Jean, PhD, proposed a big change in perspective. In their own words, here's their proposal to add "bottom up" analysis to aircraft safety certifications on Multi-Core Processors (MCP):
Topics: Avionics Multicore FAA Safety TC-16/51 CAST-32A Certification MCP
6 min read
Lynx & ENSCO Demonstrate Avionics Solutions @ DSEI JAPAN 2019
By Dan Westerberg | Senior Systems Engineer on Nov 17, 2019 7:53:00 AM
The most formidable challenges of modern avionics development programs are often centered around the safety certification process and the corresponding requirements and costs. Equally as challenging to any large development program are the design and implementation phases where the software application comes to life as it is realized on the target system environment. These phases can be compromised by
Topics: Demo Lynx MOSA.ic™ Events Embedded Blog Multicore FAA Safety Certification MCP Systems Architecture
5 min read
What is SR-IOV and Why is It Important for embedded devices?
By Tim Loveless | Principal Solutions Architect on Oct 10, 2019 7:51:00 AM
Topics: Multi-core Avionics Demo Cache-partitioning Lynx MOSA.ic™ Embedded Blog Safety MCP Systems Architecture
3 min read
Multi-core cache allocation technology (CAT) demo
By Tim Loveless | Principal Solutions Architect on Sep 20, 2019 7:51:00 AM
This week saw LYNX’s cache partitioning feature for Lynx MOSA.ic™ demonstrated for the first time at the Collins Aerospace Embedded Computing Conference in Cedar Rapids, Iowa. Cache partitioning is a new feature of Lynx MOSA.ic™ released in September 2019 and based on Intel’s Cache Allocation Technology (CAT) CPU hardware feature.